A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications

Recently, computer architectures that combine a recon gurable (or retargetable) coprocessor with a general-purpose microprocessor have been proposed. These architectures are designed to exploit large amounts of ne grain parallelism in applications. In this paper, we study the performance of the recon gurable coprocessors on multimedia applications. We compare a Field Programmable Gate Array (FPGA) based recon gurable coprocessor with the array processor called REMARC (Recon gurable Multimedia Array Coprocessor). REMARC uses a 16-bit simple processor that is much larger than a Con gurable Logic Block (CLB) of an FPGA. We have developed a simulator, a programming environment, and multimedia application programs to evaluate the performance of the two coprocessor architectures. The simulation results show that REMARC achieves speedups ranging from a factor of 2.3 to 7.3 on these applications. The FPGA coprocessor achieves similar performance improvements. However, the FPGA coprocessor needs more hardware area to achieve the same performance improvement as REMARC.